1. Field of the Invention
The present invention relates to optically-sensitive semiconductor packages and, more particularly, to an optically-sensitive semiconductor package in which a semiconductor chip can detect external light emitted into the package.
2. Description of Related Art
A conventional semiconductor device usually encapsulates a semiconductor chip with a non-transparent molding resin, which prevents the encapsulated semiconductor chip from incurring chemical reaction with external atmosphere as well as providing mechanical protection to avoid damage to the semiconductor chips from external impact. However for optically-sensitive semiconductor devices such as image-sensing or ultraviolet erasable EP-ROM packages, it is necessary for the semiconductor chip to receive external light. In order to achieve this, the structure of such optically-sensitive semiconductor device should be designed in a manner that external light is capable of reaching the inner part of the device, so that the light emitted into the device can be detected by the optically-sensitive semiconductor chip.
There are many different forms of conventional optically-sensitive semiconductor devices. One of them is shown in FIG. 4 illustrating a semiconductor device 3 which has a semiconductor chip 32 adhered onto a substrate 30 and electrically connected to the substrate 30 via gold wires 34. The semiconductor chip 32 is positioned within a frame 36, mounted on the substrate 30, and a transparent cover plate 38 is bonded to the frame 36 to hermetically separate the semiconductor chip 32 and the gold wire 34 from the atmosphere, while allowing external light to be emit to the semiconductor chip 32 encapsulated in the semiconductor device 3.
However, the structure of the semiconductor device 3 has the following drawbacks. Firstly, the overall height of the semiconductor device 3 consists of the height of the solder ball 39, the thickness of the substrate 30, and the semiconductor chip 32, the wireloop height of the gold wire 34 above the semiconductor chip 32, the distance between the top of the wireloop of the gold wire 34 and the cover plate 38, and the thickness of the cover plate 38, making it difficult to reduce. As a result, such a limitation in height can hardly meet the requirement for a low-profile semiconductor device. Further, the semiconductor chip 32, the frame 36, and the solder balls 39 are mounted on the top and the bottom surfaces of the substrate 30 respectively. As they have different coefficient of thermal expansion, the substrate 30 tends to warp during temperature cycle and reliability test due to substantial temperature variation. The occurrence of warpage of the substrate 30 will result in delamination of substrate 30 from the semiconductor chip 32, as well as loss of the planarity of the solder balls 39. Consequently, electrical connection between the solder balls 39 and an external device such as a printed circuit board cannot be completely and effectively accomplished, thereby causing the external connection capability of the semiconductor device 3 to be adversely affected.
It is therefore an objective of the present invention to provide a low-profile optically-sensitive semiconductor device that its overall thickness can be effectively reduced.
Another objective of the invention is to provide a low-profile, optically-sensitive semiconductor device that its mechanical strength can be improved such that the occurrence of delamination can be effectively prevented.
Still another objective of the invention is to provide a low-profile, optically-sensitive semiconductor device with improved heat-dissipation efficiency than the prior art.
Yet another objective of the invention is to provide a low-profile, optically-sensitive semiconductor device that the quality of electrical connection of the solder balls with external devices can be assured.
Still another objective of the invention is to provide a low-profile, optically-sensitive semiconductor device of which the thickness of and the cost of manufacturing the substrate can be effectively reduced.
In accordance with the foregoing and other objectives, the present invention proposes a novel low-profile, optically-sensitive semiconductor device. The low-profile, optically-sensitive semiconductor device comprises a substrate having an opening, a first surface, a second surface opposing the first surface, a plurality of conductive traces formed on the second surface, and a plurality of conductive vias formed through the substrate for electrically coupling to the conductive traces; a cover member attached to the first surface of the substrate for covering an end of the opening; a semiconductor chip positioned within the opening of the substrate and adhered to the cover member; a plurality of first conductive elements for electrically coupling the semiconductor chip to the conductive traces on the substrate; a first encapsulant formed on the second surface of the substrate for encapsulating the conductive traces; a sealing member attached to the first encapsulant for sealing the opening so as to hermetically separate the semiconductor chip and the first conductive elements from the atmosphere; a plurality of second conductive elements formed on the first surface of the substrate for electrically coupling to the conductive vias; and a second encapsulant formed on the first surface of the substrate in such a manner that the cover member and the second conductive elements are exposed, so as to allow the outer surface of the cover member and the terminal of each of the second conductive elements to be flush with the outer surface of the second encapsulant.
The cover member may be a silicon film, an epoxy resin tape, a polyimide tape or a film or a tape made of similar material. Alternatively, the cover plate may be a heat spreader made of heat dissipating metal such as copper, aluminum, copper alloy or aluminum alloy. For further improving heat-dissipation efficiency, a thermally-conductive adhesive may be used to adhere the semiconductor chip to the cover member.
The sealing member may be a plate made of transparent glass, plastics, or metallic materials, allowing it to cover an opening formed in the central area of the first encapsulant which interconnects the opening of the substrate. This allows the semiconductor chip and the first conductive elements to be prevented from contact with the atmosphere. A transparent resin material may also be used to fill up the openings of the substrate and the first encapsulant, so as to form as the sealing member for encapsulating the semiconductor chi and the first conductive members. As the sealing member formed by the transparent resin material is light-penetrable, the semiconductor chip can still receive and respond to external light.
The first conductive elements are preferably gold wires. Solder balls may be used as the second conductive elements such that conventional solder ball implantation methods can be utilized to electrically couple the solder balls to the conductive vias of the substrate. Note that the second conductive elements may also be in the form of connecting lumps formed by conductive metals such as copper, lead, alloy thereof or other similar metals or alloy thereof. In this case, the connecting lumps may be mounted on the first surface of the substrate by conventional printing technology, in order to electrically couple the conductive vias of the substrate. After the second conductive elements have been formed on the predetermined positions on the first surface of the substrate, the second encapsulant is then formed over the first surface of the substrate to encapsulate the second conductive elements and the cover member in such manner that the second conductive elements and the cover plate are exposed to the second encapsulant. In order to reduce the overall thickness of the devices thus-obtained, conventional grinding method can be used to grind the second encapsulant, the second conductive elements and/or the cover plate. As a result, not only the overall height of the packaged product can be effectively reduced, but also the outer surface of the second encapsulant and the exposed ends of the second conductive elements as well as the exposed surface of the cover member can be co-planar with each other.